quad line receiver AS10515F16MIL austin semiconductor, inc. AS10515F16MIL rev. 2.0 11/01 austin semiconductor, inc. reserves the right to change products or specifications without notice. 1 for more products and information please visit our web site at www.austinsemiconductor.com available as military specifications ? military equivalent screening - 883 1.2.2 quad line receiver pin assignment (top view) 16-pin flatpack (f) general description the AS10515F16MIL is a quad differential amplifier designed for use in sensing differential signals over long lines. the base bias supply (v bb ) is made available at pin 9 to make the device useful as a schmitt trigger, or in other applications where a stable reference voltage is necessary. active current sources provide the AS10515F16MIL with excellent common mode noise rejection. if any amplifier in a package is not used, one input of that amplifier must be connected to v bb (pin 9) to prevent upsetting the current source bias network. ? p d = 150mw max/pkg (no load) ? t pd = 2.0ns typ ? t r , t f = 2.0ns type (20% - 80%) function flats burn-in (condition c) v cc1 5 gnd a out 6 51 w to v tt b out 7 51 w to v tt a in \ 8 v bb a in 9 gnd b in 10 gnd b in \ 11 v bb v ee 12 v ee v bb 13 v bb c in \ 14 v bb c in 15 gnd d in 16 gnd d in \ 1 v bb c out 2 51 w to v tt d out 3 51 w to v tt v cc2 4 gnd pin assignments burn-in conditions: v tt = -2.0v max/ -2.2v min v ee = -5.7v max/ -5.2v min v bb = all pins designated for v bb must be tied together, no external voltage applied. notes 1. v bb to be used to supply bias to the AS10515F16MIL only and bypassed (when used) with 0.01 f to 0.1 f capacitor. 2. when the input pin with the bubble goes positive, the output goes negative. 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 d in\ c out d out v cc2 v cc1 a out b out a in\ d in c in c in\ v bb v ee b in\ b in a in logic diagram 4 5 6 7 10 11 12 13 2 3 14 15 9 v bb
quad line receiver AS10515F16MIL austin semiconductor, inc. AS10515F16MIL rev. 2.0 11/01 austin semiconductor, inc. reserves the right to change products or specifications without notice. 2 notes: 1. t r = t f = 2.0ns 0.2ns measured at (20% - 80%) 2. p w > 20ns 3. p rf = 1.0 mhz 4. r 1 = 50 w resistor in series with 50 w coax constituting the 100 w load. 5. unused outputs should be loaded 100 w to ground. 6. 2:1 divider may be used. figure 1. switching test circuit and waveforms d.u.t. v cc = 2.0v 0.005v 25 f 20% 0.1 f 20% coax a channel a channel b coax b r 1 c l coax *pulse generator input 0.1 f 20% v ee = -3.2v 0.005v *pulse generator must be capable of rise and fall times of 2.0ns 0.2ns. r 1 = 50 w resistor in series with a 50 w coax cable constituting the 100 w load. t r t f 80% 50% 20% 80% 50% 20% 80% 50% 20% 80% 50% 20% 80% 50% 20% 80% 50% 20% > 20ns v in v out v out \ t tlh t plh t phl t thl t thl t tlh t plh t phl ps1 ps2
quad line receiver AS10515F16MIL austin semiconductor, inc. AS10515F16MIL rev. 2.0 11/01 austin semiconductor, inc. reserves the right to change products or specifications without notice. 3 * electrical characteristics each mecl 10k series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been established. the circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained. outputs are terminated through a 100 w resistor to -2.0 volts. quiescent limit table* ** connected to pin 9. *** measure voltage on pin 9 while it is connected to other pins. v ih1 v il1 v ih2 v il2 p s1 p s2 v eel v ee v cb t a = 25c -0.78 -1.85 -1.105 -1.475 +1.11 +0.31 -3.2 -5.2 -5.2 t a = 125c -0.63 -1.82 -1.000 -1.400 +1.24 +0.36 -3.2 -5.2 -5.2 t a = -55c -0.88 -1.92 -1.255 -1.510 +1.01 +0.28 -3.2 -5.2 -5.2 test voltage values (volts) test temperature symbol parameter units min max min max min max v ih1 v il1 v ih2 v il2 v ee v cc *** p.u.t. v oh high output voltage -0.93 -0.78 -0.825 -0.63 -1.08 -0.88 v 5, 6, 11, 12 4, 7, 10, 13 8 1, 16 4 - 7 11 - 13 2, 3 ,14, 15 v ol low output voltage -1.85 -1.62 -1.82 -1.545 -1.92 -1.655 v 4, 7, 10, 13 5, 6, 11, 12 8 1, 16 4 - 7 11 - 13 2, 3 ,14, 15 v oh1 high output voltage -0.95 -0.78 -0.845 -0.63 -1.10 -0.88 v 5, 6, 11, 12 4, 7, 10, 13 8 1, 16 4 - 7 11 - 13 2, 3 ,14, 15 v ol1 low output voltage -1.85 -1.60 -1.82 -1.525 -1.92 -1.635 v 4, 7, 10, 13 5, 6, 11, 12 8 1, 16 4 - 7 11 - 13 2, 3 ,14, 15 **v bb reference voltage -1.35 -1.23 -1.24 -1.12 -1.44 -1.32 v 8 1, 16 5, 6 11, 12 9 i ee power supply current -26 -29 -29 ma 8 1, 16 5, 6 11, 12 8 i ih input current high 95 165 165 a 4 - 7 10 - 13 8 1, 16 4 - 7 10 - 13 i cbo input leakage current -1.0 -1.0 -1.5 a 8 1, 16 4 - 7 10 - 13 4 - 7 10 - 13 limits test voltage applied to pins below: pinouts referenced are for f package, check pin assignments v cc = 0v, output load = 100 w w w w to -2.0v subgroup 3 functional parameters: +25c subgroup 1 +125c subgroup 2 -55c
quad line receiver AS10515F16MIL austin semiconductor, inc. AS10515F16MIL rev. 2.0 11/01 austin semiconductor, inc. reserves the right to change products or specifications without notice. 4 * electrical characteristics each mecl 10k series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been established. the circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained. outputs are terminated through a 100 w resistor to -2.0 volts. quiescent limit table* v ih1 v il1 v ih2 v il2 p s1 p s2 v eel v ee v cb t a = 25c -0.78 -1.85 -1.105 -1.475 +1.11 +0.31 -3.2 -5.2 -5.2 t a = 125c -0.63 -1.82 -1.000 -1.400 +1.24 +0.36 -3.2 -5.2 -5.2 t a = -55c -0.88 -1.92 -1.255 -1.510 +1.01 +0.28 -3.2 -5.2 -5.2 test voltage values (volts) test temperature symbol parameter units min max min max min max v in v out v cc v eel p.u.t. t tlh rise time 1.1 3.3 1.0 4.4 1.0 3.9 ns 4, 7, 11, 13 2, 3, 14, 15 1, 16 8 2, 3 ,14, 15 t thl fall time 1.1 3.3 1.0 4.4 1.0 3.9 ns 4, 7, 11, 13 2, 3, 14, 15 1, 16 8 2, 3 ,14, 15 t phl propagation delay high to low 1.0 2.9 1.0 4.0 1.0 3.5 ns 4, 7, 11, 13 2, 3, 14, 15 1, 16 8 2, 3 ,14, 15 t plh propagation delay low to high 1.0 2.90 1.0 4.0 1.0 3.5 ns 4, 7, 11, 13 2, 3, 14, 15 1, 16 8 2, 3 ,14, 15 functional parameters: +25c subgroup 9 limits test voltage applied to pins below: pinouts referenced are for f package, check pin assignments v cc = 2.0v, output load = 100 w w w w to gnd subgroup 11 +125c subgroup 10 -55c
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